Phase locked loops are used in electronic circuitry for a variety of purposes. For example, phase locked loops are used for frequency multiplication, de-skewing, phase alignment, and a number of other applications well known to those skilled in the art.
A phase locked loop or "PLL" 10 of the prior art is illustrated in FIG. 1. A more detailed description of phase locked loops can be found in the article "Phase-Locked Loops: Applications, Performance, Measures, And Summaries 0f Analytical Results," Chak M. Chie and William C. Lindsey, Phase-Locked Loops, IEEE Press, 1985. The particular phase locked loop illustrated in FIG. 1 is used for frequency multiplication.
In FIG. 1, the PLL 10 includes an input signal 12 at a frequency f.sub.0 which is divided by a factor "M" in a divider 14 to create an input clock 16 of frequency f.sub.0 /M. The input clock 16 is one input to a comparator 18. An output 20 of comparator 18 controls a loop filter 22 which produces a control signal 24. A voltage controlled oscillator or "VCO" 26 is controlled by the control signal 24 and produces an output clock f.sub.1 having a frequency f.sub.1 =Nf.sub.0 /M. This output clock frequency f.sub.1 is, therefore, a multiple that is "N" times the input clock frequency of f.sub.0 /M. The output clock is divided by the factor "N" in a divider 28 to produce a comparison clock 30 having a frequency of f.sub.0 /M. The comparison clock 30 is compared with the input clock 16 to develop the comparator output 20.
It is apparent from the diagram of FIG. 1 that the divider 28 determines the frequency of operation of the VCO by the size of the divisor "N". Therefore, if an input clock frequency of, for example, 10 megahertz is provided, and if N=4, the output clock frequency f.sub.1 and the frequency of operation of VCO 26 will be 4 times the input clock frequency, or 40 megahertz.
In FIG. 2, a prior art VCO 26 includes four latches 32, 34, 36, and 38, which are also labeled as stages 1, 2, 3, and 4, respectively. The latches 32-28 are chained together such that (except for stage 1 ) the inputs of each stage are coupled to the outputs of the preceding stage. The output of the last stage 4 is coupled back to the inputs of stage 1. In other words, the "chain" of stages is formed into a "loop" to provide the necessary feedback ("feedback loop") for oscillation. Since an inversion is necessary for oscillation, the outputs of stage 4 are crossed before being coupled to the inputs of stage 1. Each of the latches (stages) have an inherent delay, the length of which is controlled by a VCO control signal VCO--CTL on line 24.
A problem encountered with the prior art PLL 10 is that the VCO 26 oscillates at the high frequency level f.sub.1, which is N times the input clock frequency. In the current example, if the input clock frequency is 10 megahertz, the output clock frequency f.sub.1 is 40 megahertz. Since power consumption of in an electronic circuit is directly related to its frequency of operation, this high frequency operation can be quite disadvantageous in that it causes the circuit to consume a great deal of energy. This is a particular problem with battery-powered circuitry such as with portable computers.
Moreover, as operating frequencies continue to increase, e.g. into the 100 MHz, 200 MHz, and even higher frequency ranges, the frequency of operation of PLLs will become a more universal problem. This is because, in addition to increased power consumption at higher frequencies, high frequency PLL operation further suffers from other problems, including heat generation, electromagnetic interference (EMI) generation, and the difficulty of designing and manufacturing the electronic circuitry of the PLL to operate at such high frequencies.
The above-mentioned problems with prior art PLL designs are made worse when phase-shifted clocks are also required from the PLL. For example, to provide a first 50 megahertz output clock and a second 50 megahertz clock that is one quarter of a cycle (i.e. 90 degrees) out of phase with the first output clock, a conventional PLL would have to operate its VCO at 200 megahertz. The output clock could then be divided down to obtain the two clocks. Operating a VCO at 200 megahertz will cause the PLL to exhibit many of the aforementioned disadvantages, including high energy consumption, heat production, and EMI. In addition, the PLL would tend to be expensive to manufacture due to the exotic devices and manufacturing techniques that would be required to operate the PLL at such high frequencies.